The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including a redundancy memory cell array therein.
A semiconductor memory device comprises a large number of memory cells arranged along orthogonal rows and columns. A density of defects generated in such a semiconductor memory device during manufacturing is relatively independent of the integration density of the device, but depends on semiconductor manufacturing technology. Therefore, the higher the integration density of the device, the greater the ratio of the number of normal memory cells to that of defective memory cells. This is one of the advantages obtained by increasing the integration density of a semiconductor memory device. However, even if the device has only one defective memory cell, the device cannot operate normally, and therefore is abandoned.
Previously, to operate a semiconductor memory device despite a defective memory cell, a redundancy memory cell array is incorporated with a main memory cell matrix along rows or columns thereof. Therefore, if a defective memory cell is detected, the redundancy memory cell array is used instead of the row memory cell array or the column memory cell array containing the defective memory cell. Incorporating a redundancy memory cell array in a semiconductor memory device, improves the manufacturing yield of the device.
One proposed semiconductor memory device containing a redundancy memory cell array comprises a first row address decoder means for selecting a row memory cell array within the main memory cell matrix, a second decoder means for selecting the redundancy memory cell array and a switching means for stopping the transmission of a clock signal for driving the first decoder means. The second decoder means includes a programmable read-only memory (PROM) into which a row address corresponding to the row containing the defective memory cell is written. Therefore, when the address of the defective row is supplied to the second decoder means, it selects the redundancy memory cell array and simultaneously activates the switching means disabling the first decoder means so that the defective row memory cell array is not selected. That is, the redundancy memory cell array is selected instead of the defective row memory cell array. However, in this device, since the current flowing through the switching means is relatively large, the area of switching transistors used for the switching means is large. This increases the areas of the memory device.
Another proposed semiconductor device, including the redundancy memory cell array and the first and second decoder means, comprises a disabling means in the row address decoder means instead of the above-mentioned switching means. In this device, when the defective row address is supplied to the second decoder means, the decoder means selects the redundancy memory array, and simultaneously disables each row decoder via the disabling means, so that the defective row memory cell array is not selected. That is, the redundancy memory cell array is selected instead of the defective row memory cell array. In this device, the area of the transistors used in the disabling means is relatively small, since currents flowing therethrough are small. However, a large number of such transistors are necessary, one for each row of the main memory cell matrix. As a result, the entire device is large.
On the other hand, a semiconductor memory device has been suggested in which a main memory cell matrix is divided into a plurality of sub memory cell matrixes. One row memory cell array is selected by selecting one of the sub memory cell matrixes and selecting one memory cell array among each sub memory cell matrix. In this device, the row decoders (and the column decoders) are simple and small in electrical structure.